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August 2004 rev 2.0 DDR 13-Bit to 26-Bit Registered Buffer
ASM4SSTVF16859
off. Note that RESETB should be supported with a
Features
Differential clock signals. Meets SSTL_2 class II specifications on outputs. Low voltage operation: VDD = 2.3V to 2.7V. Available in 64-pin TSSOP, 64-pin TVSOP, and 56-pin VFQFN packages.
LVCMOS level at a valid state since VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up.
Product Description
The ASM4SSTVF16859 is a universal 13/26 bit register (D F/F based), designed for 2.3V to 2.7V
In the JEDEC defined Registered DDR DIMM application, RESETB is specified to be asynchronous with respect to CLK/CLKB; therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the time to disable the differential input receivers. This ensures there are no "glitches" on any output. However, when coming out of low power standby mode, the register will become active quickly relative to the time taken to enable the differential input receivers. When the data inputs are at a logic level low and the clock is stable during the low-to-high transition of RESETB until the
VDD operation. The device supports SSTL_2 I/O levels, and is fully compliant with the JEDEC JC40, JC42.5 DDR I specifications covering PC1600, PC 2100, PC2700, and PC3200 operational ranges ( DDR 400 - 200 MHz ). 13/26 bits refers to 2Q outputs for each D input - designed for use in Stacked Registered (stacked Memory Devices), Buffered DIMM
applications.
Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive edge of CLK is used to trigger the data transfer, and CLKB is used to maintain sufficient noise margins, whereas RESETB input is designed and intended for use at power-up.
input receivers are fully enabled, the design ensures that the outputs will remain at a logic low level.
Applications
* JEDEC and Non-JEDEC DDR Memory Modules * * Stacked or Planar configurations. Supports PC1600 - PC2100 - PC2700 - PC3200 * * * DDR 400 compliant (200MHz+).
The ASM4SSTVF16859 supports a low power standby mode of operation. A logic level low at RESETB, assures that all internal registers and outputs (Q) are reset to a logic low state, and that all input receivers, data (D) buffers, and clock (CLK/CLKB) are switched
SSTL_2 I/O. Provides a complete support solution for JEDEC JC42.5 DIMMs' when used with the ASM5CVF857 Zero Delay Buffer.
Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2004 rev 2.0 Block Diagram
ASM4SSTVF16859
ASM4SSTVF16859
CLK CLKB Q1A
RESETB D1 VREF
R CLK D1
Q1B
To 12 other channels
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0 Pin Configurations
ASM4SSTVF16859
Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESETB GND CLKB CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ
ASM4SSTVF16859
43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14
ASM4SSTVF16859
42 41 40 39 38 37 36 35 34 33 32 31 30 29
64-pin TSSOP 6.10 mm body, 0.50 mm pitch
DDR 13-Bit to 26-Bit Registered Buffer
15 16 17 18 19 20 21 22 23 24 25 26 27 28
56-pin VFQFN (MLF2)
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ASM4SSTVF16859
Pin Descriptions
64-pin TSSOP Pin # 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31, 32 7, 15, 26, 34, 39, 43, 50, 54, 58, 63 6, 18, 27, 33, 38, 47, 59, 64 35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57, 61, 62 48 49 37, 46, 60 51 45 CLK CLKB VDD RESETB VREF I I P I I Positive master clock input. Negative master clock input. Core supply voltage, 2.5V nominal. Rest Active low. Input reference voltage, 1.25V nominal. GND VDDQ D(13:1) P P I Ground to entire chip. Output supply voltage, 2.5V nominal. Data input. Pin Name Q (13:1) Type O Description Data output.
56-pin MLF2
Pin # 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 50, 51, 52, 53, 54, 56 37, 48 9, 17, 23, 27, 34, 44, 49, 55 24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47 35 36 26, 33, 45 38 32 -
Pin Name Q (13:1) GND VDDQ D(13:1) CLK CLKB VDD RESETB VREF Center Pad
Type O P P I I I P I I P
Description Data output. Ground to entire chip. Output supply voltage, 2.5V nominal. Data input. Positive master clock input. Negative master clock input. Core supply voltage, 2.5V nominal. Rest Active low. Input reference voltage, 1.25V nominal. Ground (VFQFN package only)
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0 Truth Table
Inputs RESETB L H H H
Note: 1. H=High signal level, L=Low signal level, = transition from low to high,
ASM4SSTVF16859
Q Outputs CLKB X or floating D X or floating H L Q L H L Q 02
CLK X or floating
L or H
L or H
X
= transition from high to low, X = don't care
2. Output level before the indicated steady state input conditions were established.
1
Absolute Maximum Ratings
Parameter Storage Temperature Supply Voltage Input Voltage
1 1,2
Min -65 -0.5 -0.5 -0.5 50 50 50 100 55
Max +150 3.6 VDD + 0.5 VDD + 0.5
Unit C V V V mA mA mA mA C/W
Output Voltage
Input Clamp Current Output Clamp Current Continuous Output Current VDD, VDDQ or GND current/pin Package Thermal Impedance
Note:
3
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability.
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004
ASM4SSTVF16859
rev 2.0 Recomended Operating Conditions - DDRI / DDR333 (PC1600, PC2100, PC2700)*
Parameter VDD VDDQ VREF VTT VI VIH(DC) VIH(AC) VIL(DC) VIL(AC) VIH VIL VICR VID VIX IOH IOl TA Supply voltage I/O supply voltage Reference voltage Termination voltage Input voltage DC input high voltage AC input high voltage DC input low voltage AC input low voltage Input high voltage level Input low voltage level Common mode input range Differential input voltage Cross-point voltage of differential clock pair High-level output current Low-level output current Operating free-air temperature 0 RESETB CLK CLKB 1.7 0.7 0.97 0.36 (VDDQ/2) - 0.2 (VDDQ/2) +0.2 -20 20 70 1.53 Data Inputs Description Min 2.3 2.3 1.15 VREF - 0.04 0 VREF + 0.15 VREF + 0.31 VREF - 0.15 VREF - 0.31 Typ 2.5 2.5 1.25 VREF Max 2.7 2.7 1.35 VREF + 0.004 VDD Unit V V V V V V V V V V V V V V mA mA C
Recomended Operating Conditions - DDRI-400 (PC3200)*
Parameter VDD VDDQ VREF VTT VI VIH(DC) VIH(AC) VIL(DC) VIL(AC) VIH VIL VICR VID VIX IOH IOL TA Supply Voltage I/O supply voltage Reference voltage Termination voltage Input voltage DC input high voltage AC input high voltage DC input low voltage AC input low voltage Input high voltage level Input low voltage level Common mode input range Differential input voltage Cross-point voltage of differential clock pair High-level output current Low-level output current Operating free-air temperature 0 RESETB 1.7 0.7 0.97 0.36 (VDDQ/2) - 0.2 (VDDQ/2) + 0.2 -16 16 70 1.53 Data Inputs Description Min 2.5 2.5 1.25 VREF - 0.04 0 VREF + 0.15 VREF + 0.31 VREF - 0.15 VREF - 0.31 Typ 2.6 2.6 1.3 VREF Max 2.7 2.7 1.35 VREF + 0.04 VDDQ Units V V V V V V V V V V V V V V mA mA C
CLK, CLKB
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0
* Guaranteed by design. Not 100% production tested.
ASM4SSTVF16859
DC Electrical Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
TA = 0C to 70C, VDD = 2.5 0.2V, and VDDQ = 2.5 0.2V (unless otherwise stated) Guaranteed by design. Not 100% production tested.
Symbol VIK VOH
Parameters II = -18 mA
Test conditions
VDD 2.3 V 2.3 V to 2.7 V 2.3 V 2.3 V to 2.7 V 2.3 V 2.7 V 2.7 V 2.7 V 2.7 V IO = 0 2.7 V
Min
Typ
Max -1.2
Units V V V
IOH = -100 A IOH = -16 mA
VDD - 0.2 1.95 0.2 0.35 5 0.01 25 30
VOL
IOL = 100 A IOL = 16 mA
V V A A mA A/clock MHz
II IDD
All inputs
VI = VDD or GND
Standby (static) RESETB = GND Operating (static) VI = VIH(AC) or VIL(AC), RESETB = VDD RESETB = VDD, VI = VIH(AC) or 50% duty cycle RESETB = VDD, VI = VIH(AC) or switching 50% duty cycle One data input switching at half clock frequency, 50% duty cycle IOH = -20 mA IOL = 20 mA IO = 20 mA, TA = 25 C VI = VREF 310 mV, VICR = 1.25 V, VI(PP) = 360 mV CLK and CLKB RESETB VI = VDD or GND
IDDD
Dynamic only) Dynamic each data input)
operating (clock VIL(AC), CLK and CLKB switching 10
/clock MHz/data input
operating (per VIL(AC), CLK and CLKB =
rOH rOL rO(D) Ci
Output high Output low |rOH - rOL| each separate bit Data inputs
2.3 V to 2.7 V 2.3 V to 2.7 V 2.5 V 2.5 V 2.5 V 2.5V
7 7
20 20 4
W W W pF pF pF
2.5 2.5 2.5
3.5 3.5 3.5
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0 DC Electrical Characteristics - DDRI - 400 (PC3200)
TA = 0C to 70C, VDD = 2.6 0.2V, and VDDQ = 2.6 0.2V (unless otherwise stated) Guaranteed by design. Not 100% production tested. Symbol VIK VOH Parameters II = -18 mA IOH = -100 A IOH = -8 mA VOL IOL = 100 A IOL = 8 mA II IDD All inputs Standby (static) Operating (static) IDDD Dynamic operating (clock only) Dynamic each data input) rOH rOL rO(D) VI = VDD or GND RESETB = GND VI = VIH(AC) or VIL(AC), RESETB = VDD RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB switching 50% duty cycle RESETB = VDD, VI = VIH(AC) or 50% duty cycle; One data input switching at half clock frequency, 50% duty cycle Output high IOH = -16 mA Output low |rOH - rOL| each separate bit Data inputs Ci IOL = 16 mA IO = 20 mA, TA = 25 C VI = VREF 310 mV, VICR = 1.25 V, 2.5 V to 2.7 V 2.5 V to 2.7 V 2.6 V 2.6 V 2.6 V 2.6V 2.5 2.5 2.5 7 7 IO = 0 2.7 V 2.7 V Test conditions VDD 2.5 V 2.5 V to 2.7 V 2.5 V 2.5 V to 2.7 V 2.5 V 2.7 V 2.7 V 2.7 V VDD - 0.2 1.95 Min
ASM4SSTVF16859
Typ
Max -1.2
Units V V V
0.2 0.35 5 0.01 25 30
V V A A mA
A/clock MHz
10
/clock MHz/data input
operating (per VIL(AC), CLK and CLKB = switching
20 20 4 3.5 3.5 3.5
W W W pF pF pF
CLK and CLKB VI(PP) = 360 mV RESETB VI = VDD or GND
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0 Timing Requirements**
Guaranteed by design. Not 100% production tested. Symbol Parameters VDDQ = 2.5V0.2V Min fCLOCK tW tACT* tINACT* tS Clock frequency Pulse duration, CK, CKLB high or low Differential inputs active time Differential inputs inactive time Setup time, fast slew rate Setup time, slow slew rate th Hold time, fast slew rate Hold time, slow slew rate Data after CLK, CLKB Data before CLK, CLKB 0.75 0.9 0.75 0.9 2.5 22 22 Max 200
ASM4SSTVF16859
VDDQ = 2.6V0.1V Min Max 270 2.5 22 22 0.4
Units
MHz ns ns ns ns
0.6 0.4 0.6 ns
Note: 1. Data inputs must be low for a minimum time of tACT max, after which RESETB is taken high. 2. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tINACTmax after which RESETB is taken low. 3. For data signal input slew rate >=V/ns 4. For data signal input slew rate >=0.5 V/ns and < 1V/ns 5. CLK,CLKB signals input slew rates are >=1V/ns
Switching Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)**
Symbol From (input) To (output) VDD = 2.5 V 0.2 V Min fmax tPD CLK, CLKB (TSSOP) CLK, CLKB (VFQFN[MLF2]) tphl RESETB Q Q Q 200 1.1 1.1 - - Typ - Max - 2.8 2.8 5.0 MHz ns ns ns Units
Switching Characteristics - DDRI-400 (PC3200)**
Symbol From (input) To (output) VDD = 2.6 V 0.1 V Min fmax tPD tPDSS tphl RESETB CLK, CLKB (VFQFN[MLF2]) Simultaneous switching Q Q 2.48 3.5 ns ns Q 210 1.1 2.2 Typ Max MHz ns Units
*this parameter is not necessarily production tested. **Over recommended operating free-air temperature range unless otherwise noted.
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0
Parameter Measurement Information (VDD = 2.5 V 0.2 V)
ASM4SSTVF16859
VTT RL = 50 From output under test Test point CL = 30 pF Load circuit
1 1
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ/2. VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. tPLH and tPHL are the same as tpd. Input active and inactive times LVCMOS RESETB VDD 0V 90% 10%
1
Input
IDD
1
VDD /2 tinact
VDD /2 tact
IDDH IDDL
IDD tested with clock and data inputs held at V or GND, and IO = 0 mA. DD
Pulse duration
tw Input VREF VREF VIH VIL
Setup and hold times
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0
VI(pp) Timing input ts Input VREF VICR th VREF VIH VIL
ASM4SSTVF16859
Propagation delay times
VI(pp) Timing input VICR tPLH Output VTT VICR tPHL VTT VOH VOL
LVCMOS RESETB Input VDD /2 tPHL Output VTT
VIH VIL VOH VOL
Output slew rates over recommended operating free-air temperature range (unless otherwise noted) VCC= 2.5 V + 0.2V * Min dV/dt_r dV/dt_f dV/dt_
Parameter
From 20% 80% 20% or 80%
To 80% 20% 80% or 20%
VCC = 2.6 V + 0.1 V * Min 1 1 Max 4 4 1
Unit V/ns V/ns V/ns
Max 4 4 1
1 1
*For this test condition, VDDQ is always equal to VDD **Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
DDR 13-Bit to 26-Bit Registered Buffer
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ASM4SSTVF16859
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0 Package Dimensions (64- Pin TSSOP)
ASM4SSTVF16859
N
c L
Symbol
Millimeters Min Max 1.20 0.15 1.05 0.27 0.20
Inches Min - 0.002 0.32 0,007 0.0035 Max 0.047 0.006 0.041 0.011 0.008
E1 Index area 12 D A2 e b A1
E
A A1 A2 b
- 0.05 0.80 0.17 0.09
A
Seating plane
c D E E1 e
See variations below 8.10 basic 6.00 6.20 0.319 basic 0.236 0.244
aaa C
0.50 basic 0.45 0.75
0.020 basic 0.018 0.030
6.10 mm (240 mil) body, 0.50 mm (0.020 mil) pitch TSSOP
L N a aaa Variations:
See variations below 0 - 8 0.10 0 - 8 0.004
D (mm) N Min 64 16.90 Max 17.10
D (inch) Min 0.665 Max 0.673
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0
ASM4SSTVF16859
Package Dimensions (56-Pin MLF2)
D D/2 D1 D1/2 0.18 Dia.
0.25 C A A 0.25 C B A2 A1 A3
E1
E
Symbol
Common dimensions Min Typ 0.85 0.00 0.01 0.65 0.20 BSC 8.00 BSC 7.75 BSC 8.00 BSC 7.75 BSC 12 0.24 0.13 0.42 0.17 0.60 0.23 Max 1.00 0.05 0.80
A E1/2 E/2 A1 A2 0.20 C B 0.20 C A Top view
Seating plane Side view
A3 D D1 E E1 q
4x P D2
0.25 C A B D2/2 Pin ID
P R
4x P e
0.35
Pitch variation D 0.50 BSC 56 14 14 0.30 0.18 0.00 4.35 0.40 0.23 0.20 4.50 0.50 0.30 0.45 4.65 5.35
N E2 Nd Ne L
(Ne - 1) X e
E2/2 L e (Nd - 1) X e
b Q D2 E2 Bottom view
5.05 b 5.20
A1 T erminal tip For odd terminal/side For even terminal/side Cross section
DDR 13-Bit to 26-Bit Registered Buffer
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ASM4SSTVF16859
Ordering Information
Ordering Number ASM4SSTVF16859-64TT ASM4SSTVF16859-64TR ASM4SSTVF16859-56QT ASM4SSTVF16859-56QR
Marking AS4SSTVF16859T AS4SSTVF16859T AS4SSTVF16859Q AS4SSTVF16859Q
Package 64-Pin TSSOP, Tube 64-Pin TSSOP, Tape & Reel 56-pin MLF2 - VQFN, Tube 56-pin MLF2 - VQFN, Tape & Reel
Qty per Reel
Temperature 0C to 70C
2500
0C to 70C 0C to 70C
2500
0C to 70C
DDR 13-Bit to 26-Bit Registered Buffer
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August 2004 rev 2.0
ASM4SSTVF16859
Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright y Alliance Semiconductor All Rights Reserved Advance Information Part Number: ASM4SSTVF16859 Document Version: v2.0
(c) Copyright 2004 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
DDR 13-Bit to 26-Bit Registered Buffer
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